This invention relates to output buffers, and more particularly to high performance output buffers with built-in ESD protection. The term output buffer, as used herein, refers to all circuits that buffer electrical signals including amplifying and non-amplifying circuits or devices.
Moore""s Law, which is named after Gordon Moore, the founder of Intel Corporation, states that the speed and density of computers will double every 18-24 months. For the most part, Moore""s Law has held true since the early days of the microprocessor, and is predicted to do so for at least another twenty years.
A corollary to Moore""s Law is that the size of the transistors used on an integrated circuit must shrink by a factor of two every 18-24 months. Until recently, this was accomplished by simply scaling bulk MOSFET devices. However, as the transistor channel lengths scale below about 0.25 um, a number of transistor effects begin to degrade the transistor""s characteristics. Some of these effects include short-channel effects, gate resistance effects, channel profiling effects and other effects. It has been found that reducing the power supply voltage can reduce some of these effects. However, reducing the power supply voltage can also severely impact the performance of the MOSFET devices.
One approach for overcoming many of these limitations is to use a Silicon-On-Insulator (SOI) substrate. SOI has significant advantages over bulk CMOS including lower power consumption, lower leakage current, lower capacitance, good sub-threshold IV characteristics, lower soft error rates for both alpha particles and cosmic rays, etc. These advantages make SOI an ideal technology for high performance, low voltage applications.
Another advantage of SOI is that the body of each transistor can be separately controlled. As discussed in xe2x80x9cHigh Speed SOI Buffer Circuit with the Efficient Connection of Subsidiary MOSFET""s for Dynamic Threshold Controlxe2x80x9d, Lee et al., Proceedings 1997 IEEE International SOI Conference, October 1997, page 152, this allows the threshold voltage of each transistor to be dynamically controlled, particularly at low supply voltages. Dynamically adjusting the threshold voltages can significantly increase the performance that can be achieved at low supply voltages.
One of the challenges for providing viable SOI devices is the need to provide adequate electrostatic discharge (ESD) protection. ESD is an increasingly significant problem in integrated circuit design, and in particular, SOI integrated circuit design. Potentially destructive electrostatic pulses, which are known as ESD events, are typically caused by various transient sources such as human or machine handling of the integrated circuit chip during processing, assembly and installation. Most ESD events originate at one of the integrated circuit pads. Since output buffers are typically connected to an integrated circuit pad, it is desirable to provide some sort of ESD protection to the output buffer circuitry.
A typical ESD event includes a high voltage pulse to the output pad, resulting in a high discharge current path through one of the PMOS or NMOS transistors of the output buffer to Vdd or Vss, respectively. For the NMOS transistor, and depending upon the polarity of the ESD voltage pulse supplied to the pad, the discharge path may proceed either via an avalanche breakdown of the drain/body junction or via the forward biasing of the drain/body diode. The avalanche breakdown type of discharge path is the most destructive since it is most likely to result in irreversible damage to the structure of the NMOS transistor. A similar discharge path may exist through the PMOS transistor.
Several approaches for providing ESD protection to SOI CMOS integrated circuits are discussed in xe2x80x9cCMOS-On-SOI ESD Protection Networksxe2x80x9d, Voldman et al., EOS/ESD Symposium 96-291, page 6.5.1, and xe2x80x9cDynamic Threshold Body- and Gate-Coupled SOI ESD Protection Networksxe2x80x9d, Voldman et al., EOS/ESD Symposium 97-211, page 3A.2.2. A limitation of many of these prior art approaches is that one or more dedicated devices must be provided to implement the ESD protection function. These dedicated ESD devices are often relatively large, and thus consume a substantial amount of area. Further, the dedicated ESD devices are typically pre-fabricated in and around the perimeter of the device near the I/O pads, and thus are not part of the sea-of-transistors or sea-of-gates region of the integrated circuit. Instead, and as indicated above, they are typically fabricated into the under-layers of the outer perimeter of the integrated circuit, regardless of whether they are actually used in a particular Application Specific Integrated Circuit (ASIC) personality or configuration.
What would be desirable, therefore, is an output buffer with built-in ESD protection, wherein the ESD protection is provided at least in part by selected transistors in the sea-of-transistors or sea-of-gates region of the integrated circuit. This may eliminate the need for at least some of the dedicated xe2x80x9cESDxe2x80x9d devices, and in particular, those dedicated ESD devices that are pre-fabricated into the under-layers in and around the perimeter of the integrated circuit. An advantage of such an approach is that only those transistors that are actually needed to provide the desired ESD protection for the particular ASIC personality or configuration are used, thereby maximizing the overall density of the integrated circuit.
The present invention overcomes many of the disadvantages of the prior art by providing an output buffer with built-in ESD protection, wherein the ESD protection is implemented at least in part from selected transistors in the sea-of-transistors or sea-of-gates region of the integrated circuit. This may eliminate the need for dedicated xe2x80x9cESDxe2x80x9d devices, and in particular, those dedicated ESD devices that are pre-fabricated into the under-layers in and around the perimeter of the integrated circuit.
In a first illustrative embodiment of the present invention, a high performance CMOS buffer is provided with a first p-channel transistor and a first n-channel transistor connected in series between a power supply voltage and ground. The gate of the first p-channel transistor and the gate of the first n-channel transistor are coupled to the input terminal of the CMOS buffer. To increase the speed and to ensure that the body of the first p-channel transistor does not float, a first coupler circuit is provided. The first coupler circuit couples the body of the first p-channel transistor to the output terminal of the CMOS buffer when the gate of the first p-channel transistor is low, and couples the body of the first p-channel transistor to the power supply terminal of the CMOS buffer when the gate of the first p-channel transistor is high.
Likewise, to increase the speed and to ensure that the body of the first n-channel transistor does not float, a second coupler circuit is provided. The second coupler circuit couples the body of the first n-channel transistor to the output terminal of the CMOS buffer when the gate of the first n-channel transistor is high, and couples the body of the first n-channel transistor to the ground terminal of the CMOS buffer when the gate of the first n-channel transistor is low.
Preferably, the first coupler circuit includes a second p-channel transistor and a second n-channel transistor. The source and body of the second p-channel transistor is preferably coupled to the power supply terminal of the CMOS buffer. The drain of the second p-channel transistor is preferably coupled to the body of the first p-channel transistor. Finally, the gate of the second p-channel transistor is preferably coupled to the input terminal of the CMOS buffer. The source of the second n-channel transistor is preferably coupled to the body of the first p-channel transistor. The body and drain of the second n-channel transistor are preferably coupled to the output terminal of the CMOS buffer. Likewise, the gate of the second n-channel transistor is preferably coupled to the input terminal of the CMOS buffer.
The second coupler circuit preferably includes a third p-channel transistor and a third n-channel transistor. The drain of the third p-channel transistor is preferably coupled to the body of the first n-channel transistor. The body and source of the third p-channel transistor are preferably coupled to the output terminal of the CMOS buffer. The gate of the third p-channel transistor is preferably coupled to the input terminal of the CMOS buffer. Finally, the source and body of the third n-channel transistor are preferably coupled to the ground terminal of the CMOS buffer. The drain of the third n-channel transistor is preferably coupled to the body of the first n-channel transistor. The gate of the third n-channel transistor is preferably coupled to the input terminal of the CMOS buffer.
To help provide ESD protection to the CMOS buffer, a third coupler circuit may also be provided. The third coupler circuit preferably couples the gate of the first n-channel transistor to the output terminal of the CMOS buffer when the voltage at the output terminal of the CMOS buffer exceeds the voltage of at power supply terminal by a predetermined amount. This causes the first n-channel transistor to turn on when an ESD event drives the output terminal of the CMOS buffer higher than Vdd, thereby providing a path for the ESD current to the Vss power supply.
When the third coupler circuit is used in conjunction with the second coupler circuit discussed above, the body and gate of the first n-channel transistor are both coupled to the Vout terminal of the CMOS buffer when an ESD event drives Vout higher than Vdd. Preferably, the third p-channel transistor of the second coupler circuit turns on when Vout goes above Vdd by a threshold voltage, thereby connecting the body of the first n-channel transistor to Vout. Likewise, the third coupler circuit couples the gate of the first n-channel transistor to Vout of the CMOS buffer when the voltage at Vout exceeds Vdd by a predetermined amount. Thus, both the body and gate of the first n-channel transistor are coupled to the Vout terminal of the CMOS buffer when an ESD event drives Vout higher than Vdd by a predetermined amount.
This has a number of advantages. First, there is little or no voltage drop between the gate, body, source and drain of the first n-channel transistor during an ESD event. Therefore, there is little chance of stressing the thin gate oxide of the first n-channel transistor during the ESD event. Also, the voltage that can be applied at Vout without causing destructive breakdown phenomena is maximized. Destructive breakdown often results from concentrated dissipation heating, rather than spreading the heat over the full device area. Accordingly, Vout should be able to rise to the gate-to-source breakdown voltage before causing any significant catastrophic damage to the device. Another advantage is that because the gate and body are at about the same potential, the threshold voltage of the first n-channel transistor is minimized, and the bipolar current of the parasitic bipolar transistor of the first n-channel transistor is maximized. Both of these help provide a low resistance path to Vss during an ESD event.
It is contemplated that a fourth coupler circuit may also be provided. The fourth coupler circuit may couple the gate of the first p-channel transistor to the output terminal of the CMOS buffer when the voltage at the output terminal of the CMOS buffer drops below the voltage at the ground terminal by a predetermined amount. Like the third coupler circuit, the fourth coupler circuit causes the first p-channel transistor to turn on when an ESD event drives the output terminal of the CMOS buffer below Vss, thereby providing a low resistance path to the Vdd power supply.
When the fourth coupler circuit is used in conjunction with the first coupler circuit discussed above, the body and gate of the first p-channel transistor are both coupled to the Vout terminal of the CMOS buffer when an ESD event drives Vout lower than Vss. Preferably, the second n-channel transistor of the first coupler circuit turns on when Vout drops below Vss by a threshold voltage, thereby connecting the body of the first p-channel transistor to Vout. Likewise, the fourth coupler circuit preferably couples the gate of the first p-channel transistor to Vout of the CMOS buffer when the voltage at Vout drops below Vss by a predetermined amount. Thus, both the body and gate of the first p-channel transistor are coupled to the Vout terminal of the CMOS buffer when an ESD event drives Vout below Vss by a predetermined amount. This has the same advantages as discussed above.
A fifth coupler circuit may also be provided. The fifth coupler circuit may be used to prevent feedback from Vout to Vdd when an ESD event causes Vout to rise above Vdd. In some applications, it may be desirable to prevent the first p-channel transistor from turning on when Vout rises above Vdd. This is primarily because the ESD event could actually power up the circuit that is biasing the output buffer input terminal (IN) to a state which could reduce the effectiveness of the protection circuit. Accordingly, it is contemplated that the fifth coupler circuit may couple the gate of the first p-channel transistor to the output terminal of the CMOS buffer when the voltage at the output terminal of the CMOS buffer exceeds Vdd by a predetermined amount. This helps keep the first p-channel off when Vout exceeds Vdd. It is contemplated that the first, second, third, fourth and fifth coupler circuits may be used together, separately, or in any combination, depending on the desired result and/or application.
It is also contemplated that the gate of the first p-channel transistor and the gate of the first n-channel transistor may be driven by a common buffer. Alternatively, it is contemplated that the gate of the first p-channel transistor may be driven by a first buffer, and the gate of the first n-channel transistor may be driven by a second buffer. In this later case, both the first buffer and second buffer may be conventional inverter type buffers having an input terminal, an output terminal, a power supply terminal and a ground terminal. As the gate of the first n-channel transistor is driven above Vdd by, for example the third coupler circuit, the p-channel transistor of the second buffer may provide a diode to Vdd. This tends to limit the gate voltage that can be applied to the first n-channel transistor, and may cause Vdd to become charged up. While this may be beneficial for preventing gate-to-source breakdown, it may reduce the potential maximum drive of the first n-channel transistor during an ESD event. A similar scenario may occur relative to the gate of the first p-channel transistor.
To overcome these limitations, it is contemplated that the power supply terminal of the first buffer and the power supply terminal of the second buffer may be coupled to a Vdd1 power supply terminal of a Vdd1 power supply circuit. The Vdd1 power supply circuit preferably provides Vdd to the Vdd1 power supply terminal when Vout is below Vdd, and preferably provides Vout to the Vdd1 power supply terminal when Vout exceeds Vdd by a predetermined amount. This may allow the gate voltage of the first p-channel transistor and the first n-channel transistor to more effectively track Vout.
It is also contemplated that the source and body of the second p-channel transistor of the first coupler circuit may be coupled to the Vdd1 power supply terminal of the Vdd1 power supply circuit. This may help keep the source, body and drain of the second p-channel transistor at the same or similar voltage during an ESD event. If the source and body of the second p-channel transistor are coupled to Vdd, as described above, a conduction path exists from Vout to Vdd via the drain-to-body diode. This conduction path may be desirable in some applications. However, for those applications where it is not desirable, connecting the source and body of the second p-channel transistor to the Vdd1 power supply terminal of the Vdd1 power supply circuit may tend to reduce the amount of ESD current that is conducted to Vdd.
Likewise, it is contemplated that the ground terminal of the first buffer and the ground terminal of the second buffer may be coupled to a Vss1 power supply terminal of a Vss1 power supply circuit. The Vss1 power supply circuit preferably provides Vss to the Vss1 power supply terminal when Vout is above Vss, and provides Vout to the Vss1 power supply terminal when Vout drops below Vss by a predetermined amount.
It is also contemplated that the source and body of the third n-channel transistor of the second coupler circuit may be coupled to the Vss1 power supply terminal of the Vss1 power supply circuit. This may help keep the source, body and drain of the third n-channel transistor at the same or similar voltage during an ESD event. If the source and body of the third n-channel transistor are coupled to Vss, as described above, a conduction path exists from Vout to Vss via the drain-to-body diode. This conduction path may be desirable in some applications. However, for those applications where it is desirable to reduce the ESD current to Vss, connecting the source and body of the third n-channel transistor to the Vss1 power supply terminal of the Vss1 power supply circuit may tend to reduce the amount of ESD current that is conducted to Vss.
For some applications, such as cold spare applications, it is desirable to provide a CMOS buffer with a tri-state output. When in cold spare mode, the CMOS buffer is not generally powered up (Vdd=0) and the output of the driver should be tri-stated so as to not interfere with other signals on the bus. Further, the ESD protection circuitry should not effect the CMOS buffer circuit when the output is within the range of expected bus voltages.
In an illustrative embodiment, this is accomplished by providing a first nand gate, a second nand gate, a first nor gate and a second nor gate. A tri-state-bar input terminal is provided on the CMOS buffer, and an inverter generates a tri-state signal for internal use. The first input terminal of the first nand gate is preferably coupled to the input terminal of the CMOS buffer and the second input terminal of the first nand gate is preferably coupled to the tri-state-bar terminal of the CMOS buffer. Like above, the Vdd power supply terminal of the first nand gate may be coupled to the Vdd1 power supply terminal of a Vdd1 power supply circuit, and the Vss power supply terminal of the first nand gate may be coupled to a Vss1 power supply terminal of a Vss1 power supply circuit. The Vdd1 power supply circuit and the Vss1 power supply circuit are preferably similar to that described above.
The first input terminal of the second nand gate is preferably coupled to the input terminal of the CMOS buffer and the second input terminal of the second nand gate is preferably coupled to the tri-state-bar terminal of the CMOS buffer. The Vdd power supply terminal of the second nand gate is preferably coupled to the Vdd1 power supply terminal of the Vdd1 power supply circuit, and the Vss power supply terminal of the second nand gate is preferably coupled to the output terminal of the CMOS buffer.
The first input terminal of the first nor gate is preferably coupled to the input terminal of the CMOS buffer and the second input terminal of the first nor gate is preferably coupled to the tri-state signal provided by the inverter. The Vdd power supply terminal of the first nor gate is preferably coupled to the Vdd1 power supply terminal of the Vdd1 power supply circuit, and the Vss power supply terminal of the first nor gate is preferably coupled to the Vss1 power supply terminal of the Vss1 power supply circuit.
Finally, the first input terminal of the second nor gate is preferably coupled to the input terminal of the CMOS buffer and the second input terminal of the second nor gate is coupled to the tri-state signal provided by the inverter. The Vdd power supply terminal of the second nor gate is preferably coupled to the output terminal of the CMOS buffer, and the Vss power supply terminal of the second nor gate is preferably coupled to the Vss1 power supply terminal of the Vss1 power supply circuit.
A first p-channel transistor and a first n-channel transistor are preferably provided for driving the output terminal of the CMOS buffer. The source of the first p-channel transistor is preferably coupled to the power supply terminal of the CMOS buffer. The gate of the first p-channel transistor is preferably coupled to the output terminal of the first nand gate. The body of the first p-channel transistor is coupled to the output terminal of the second nand gate.
The source of the first n-channel transistor is preferably coupled to the ground terminal of the CMOS buffer. The gate of the first n-channel transistor is preferably coupled to the output of the first nor gate. Finally, the drain of the first n-channel transistor is preferably coupled to the drain of the first p-channel transistor and further coupled to the output terminal of the CMOS buffer. The body of the first n-channel transistor is preferably coupled to the output terminal of the second nor gate.
The typical requirement for the cold spare function is that both the first p-channel transistor and the first n-channel transistor remain off for Vout less than the specified maximum output buss voltage (Vddbmax). As long as input signal of the CMOS buffer or the tristate_bar signal are low, as they would normally be in the powered down cold spare mode, the Vdd1 power supply circuit pulls the gate and body of first p-channel transistor high with Vout, thereby keeping the first p-channel transistor off and preventing any significant currents between Vout and Vdd. However, to keep the first n-channel transistor off, the tri-state signal must rise with Vout to keep the gate and body of the first n-channel transistor near ground. This is preferably accomplished by connecting the power supply terminal of the tri-state inverter to a second Vdd2 power supply circuit.
The second Vdd2 power supply circuit preferably couples the Vdd2 power supply terminal of the second Vdd2 power supply circuit to Vdd when Vout is below Vdd. The second Vdd2 power supply circuit also preferably couples the Vdd2 power supply terminal of the second Vdd2 power supply circuit to Vout when the voltage at Vout is below a predetermined maximum value but above Vdd. Finally, the second Vdd2 power supply circuit preferably couples the Vdd2 power supply terminal of the second Vdd2 power supply circuit to ground when Vout is above the predetermined maximum value. The predetermined maximum value preferably corresponds to the expected maximum output buss voltage (Vddbmax).
In some cases it is desirable to allow Vout to go below Vss without introducing additional loading. In an illustrative embodiment, this is accomplished by connecting a second Vss2 power supply circuit to the gate from which tristate_bar is generated. The second Vss2 power supply circuit is similar to the second Vdd2 power supply circuit described above. That is, the second Vss2 power supply circuit preferably couples the Vss2 power supply terminal of the second Vss2 power supply circuit to Vss when Vout is above Vss, and coupled the Vss2 power supply terminal of the second Vss2 power supply circuit to the output terminal of the CMOS buffer when Vout drops below Vss but above a predetermined minimum value. Finally, the second Vss2 power supply circuit preferably couples the Vss2 power supply terminal of the second Vss2 power supply circuit to the ground terminal of the CMOS buffer when Vout drops below the predetermined minimum value.